1. Field of the Invention
The present invention relates to integrated circuits, and more particularly to insulated-gate field-effect transistors.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate electrode to control a channel region between a source and drain. The channel region, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the channel region and the substrate. The gate electrode is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate electrode, which sets up a transverse electric field in order to modulate the longitudinal conductance of the channel.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon as the gate electrode in place of aluminum. Since polysilicon has the same high melting point as a silicon substrate, it can be deposited prior to source and drain formation, and serve as a mask during formation of the source and drain by ion implantation. Thereafter, the implanted dopant is activated using a high-temperature anneal that would otherwise melt the aluminum. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate electrode and the source and drain. The resistance of polysilicon can be further reduced by forming a silicide on its top surface.
As IGFET dimensions are reduced, the maximum lateral electric field in the channel region near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device.
A number of techniques have been utilized to reduce hot carrier effects. One such technique is a lightly doped drain (LDD). The LDD reduces hot carrier effects by reducing the maximum lateral electric field. The drain is typically formed by two ion implants. A light implant is self-aligned to the gate electrode, and a heavy implant is self-aligned to the gate electrode on which sidewall spacers have been formed. The spacers are typically oxides or nitrides. The purpose of the lighter first dose is to form a lightly doped region of the drain (or LDD) at the edge near the channel region. The second heavier dose forms a low resistivity region of the drain, which is subsequently merged with the lightly doped region. Since the heavily doped region is farther away from the channel region than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics. A lightly doped region is not necessary for the source (unless bidirectional current is used), however lightly doped regions are typically formed for both the source and drain to avoid the need for an additional masking step.
Junction isolation typically refers to devices that are isolated by an oxide along the sidewalls and by a PN junction at the bottom. Junction isolation, however, is often not suitable for high-voltage applications and high-radiation environments. Silicon-on-insulator (SOI) refers to a group of technologies that provide a uniform insulating layer beneath a semiconducting layer, so that devices can be isolated by completely surrounding them with an insulator. SOI also reduces parasitic capacitance between adjacent devices.
Furthermore, as gate oxide thickness is reduced, the doping levels in the channel regions must be increased in order to maintain proper threshold voltages. Transistors with too low a threshold voltage do not turn off properly and may sustain a significant leakage current even with zero volts applied to the gate electrode. This leakage places a lower limit on the threshold voltage reductions which may be made as operating voltages are reduced to 2.7 volts or 1.8 volts. As the difference between the threshold voltage and the operating voltage is reduced, drive currents are also reduced. Another advantage of SOI is that it limits the depletion depth of the channel region, thereby improving the drive current for a given operating voltage.
SIMOX (Separation by IMplanted OXygen) is a form of SOI. SIMOX includes implanting oxygen into a silicon substrate, and then heating the substrate so that implanted oxygen and silicon react to form a buried layer of silicon dioxide. SIMOX typically involves a high dose (e.g., 2.times.10.sup.18 atoms/cm.sup.2) of atomic oxygen ions (O+) implanted at a very high energy (e.g., 150 to 180 kiloelectron-volts) so that the peak of the oxygen implant is sufficiently deep within the silicon substrate. Special oxygen implanters have been marketed, for instance, by Eaton Corp. under model numbers NV-10 and Nova-100. The silicon substrate is normally heated to at least 400.degree. C. during the high-dose implantation step to reduce disruptions to surface crystallinity. After implantation occurs, typically a high-temperature anneal (e.g., 1100 to 1175.degree. C.) is performed in a neutral ambient (e.g., N.sub.2) for a considerable length of time (e.g., 3 to 5 hours). As a result, the implanted oxygen and the silicon substrate react to form a continuous layer of stoichiometric silicon dioxide that is buried in the substrate. The buried oxide layer typically has a maximum thickness of 5000 angstroms and is buried 1000 to 3000 angstroms beneath the top of the substrate. Typically an additional layer of epitaxial silicon is deposited on the substrate so that single-crystal device regions at least 5000 angstroms thick are available for device fabrication. See, for instance, SILICON PROCESSING FOR THE VLSI ERA, Volume 2: Process Integration, by S. Wolf, published by Lattice Press, Sunset Beach, Calif., pp. 72-75 (1990), which is incorporated herein by reference.
SIMOX offers other advantages. For instance, SIMOX can reduce diffusion of channel dopants into the underlying substrate and vice-versa. SIMOX can also reduce undesired deep channel currents between the source and drain. In addition, SIMOX can reduce depletion capacitance since silicon dioxide has a smaller dielectric coefficient than silicon. These advantages are typically enhanced as the SIMOX beneath the channel region gets closer to the top surface of the substrate. However, in conventional practice, SIMOX is formed uniformly across the entire semiconductor substrate prior to device fabrication. As a result, conventional SIMOX beneath the channel region is incapable of getting closer than the bottom surfaces of the source and drain to the top surface of the substrate. Needless to say, it would be desirable to provide an IGFET with a buried insulative layer that overcomes these limitations.